1. Field of the Invention
The present invention relates to plasma processing methods, and more specifically, to plasma processing methods suitable for subjecting semiconductor substrates to surface treatments using plasma. The present invention also relates specifically to plasma processing methods suitable for forming gate electrodes in MOS (metal oxide semiconductor) transistors using photolithography.
2. Description of the Related Art
Generally, photolithography techniques are applied in the process of manufacturing semiconductors. Photolithography techniques are composed of the following steps. First, a photoresist material is applied on laminated thin film layers disposed on a semiconductor substrate, which is exposed to ultra violet rays in an exposure apparatus. Thereby, the circuit pattern of a photoresist mask is transferred onto the photoresist material via exposure, which is then developed. Thereafter, the desired circuit pattern is formed via an etching process using plasma. In the exposure process of the photolithography technique, ultraviolet rays and the like used for exposing the resist material must reach the bottom of the resist material with sufficient optical intensity, but due to standing waves caused by reflection at the thin film surface or diffused reflection at the stepped portions of the thin film, drawbacks such as exposure of unnecessary portions of the photoresist material and uneven exposure occur. When the photoresist material is developed, undesirable roughness is formed on the surface and side walls of the formed circuit pattern of the photoresist. Further, undesirable roughness occurs to the surface and side walls of the resist due for example to uneven resist polymer size, aggregation of polymers having different polarities and uneven oxygen diffusion according to chemical amplification reaction.
Furthermore, a plasma processing apparatus is generally used for the etching process for transferring the developed photoresist circuit pattern to the laminated thin film disposed below the photoresist. The plasma processing apparatus is composed for example of a vacuum processing chamber, a gas supply unit connected thereto, a vacuum unit for maintaining the pressure within the vacuum processing chamber to a desirable value, an electrode on which the material to be processed, or semiconductor substrate, is placed, and a plasma generating means for generating plasma in the vacuum processing chamber, wherein the etching of the material to be processed placed on the substrate-placing electrode is performed by generating plasma from the processing gas supplied into the vacuum processing chamber through a shower plate or the like via a plasma generating means.
These etching processes are largely classified into, for example, substrate silicon etching for forming isolations and trench capacitors, insulating film etching for forming contact holes and trenches, polysilicon etching or silicide etching for forming gate electrodes of MOS transistors, metal layer etching or high-k gate insulating film etching for forming high-k/metal gate transistors, and metal etching for forming wires.
Japanese Patent Application Laid-Open Publication No. 2001-308076 (patent document 1) discloses a method for forming ultrafine gate electrodes using a photolithography technique in the process of manufacturing semiconductors. According to the document, an insulation film, a conductive layer and an organic material layer are formed on a semiconductor substrate, a first mask pattern of a mask size β is formed on the organic material layer using photolithography, the organic material layer is etched with a mixed gas of Cl2 and O2, the first mask pattern is shrunk to form a second mask pattern of a mask size γ(<β), and the conductive layer is etched using the second mask pattern to obtain gate electrodes of a size smaller than the mask size β.
As described above, undesirable roughness is formed on the surfaces and side walls of the photoresist circuit pattern formed via a general photolithography technique. When the photoresist circuit pattern having such roughness is used as the mask to etch laminated thin films disposed below the mask in a plasma etching apparatus, there occurs a drawback in that undesirable roughness is formed on the side walls of the etched thin films similar to the roughness formed on the surfaces and side walls of the photoresist. For example, in the processing of gate electrodes of a MOS transistor in the process of manufacturing semiconductors, the roughness on the surface of the photoresist is transferred to the side walls of the polysilicon layer during etching of the polysilicon layer, and roughness of a few nm is formed on the side walls of the polysilicon layer. In the prior art gate electrode in which the gate length is a few hundred nm or longer, roughness of a few nm on the side walls of the polysilicon layer rarely affected the performance of the MOS transistor. However, along with the scaling down of the LSI (large scale integration), the gate length has been reduced to the order of tens of nm, according to which the roughness of a few nm on the side walls of the polysilicon layer transferred via the etching process could not be tolerated, since it affects the performance of the MOS transistor greatly.
Actually, a roughness of a few nm on the side walls of the polysilicon layer causes the gate length of the transistor to be reduced locally in some areas, causing a short channel effect, which leads to the increase of leak current and decrease of threshold voltage. Moreover, according to the operation properties of multiple transistors, the roughness of a few nm formed on the side walls of the polysilicon layer causes dispersion of gate length, which leads to fluctuation of transistor performances and deterioration of yield. Such roughness on the sides of the lines of the pattern is called LER (line edge roughness), and the roughness of the line width is called LWR (line width roughness), which affect the semiconductor device properties greatly.
The problems related to LER and LWR in the process of etching polysilicon electrodes of MOS transistors have been described above, but similar problems exist in processing high-k/metal gate structures and three-dimensional MOSFET, such as FIN-FET, which are considered as the structures of next-generation MOSFET transistors.
Furthermore, as the LSI size is scaled down, dry ArF exposure and immersion ArF exposure using argon fluoride laser radiation are used for photolithography, and in the future, the applications of double patterning techniques and EUV (extreme ultra violet) exposure are proposed. In order to cope with such exposure techniques, the molecular structures of photoresist materials are being improved with respect to the exposure light source. However, such improvement in molecular structures causes new drawbacks, such as deterioration of the tolerance of the photoresist mask pattern to plasma etching and insufficient initial film thickness. Such deterioration of the tolerance of the mask pattern to plasma etching or insufficient initial film thickness may cause LER and LWR, which are considered to have even greater impact on the semiconductor device performances when the speed in which the size of the semiconductor devices is scaled down is accelerated.
The influences of the LER and LWR on the forming of gate electrodes in MOS transistor shave been described as an example, but the problems of LER and LWR occur similarly in the art of hole processing, deep trench processing, STI processing, damascene processing and the like, which have drawbacks in that the circuit pattern cannot be etched with high accuracy and that a semiconductor device with a predetermined performance cannot be manufactured.
Especially, a typical example of the problems of LER and LWR regarding the etching of insulating films using fluorocarbon plasma is the generation of striation caused by plasma damage of the resist mask for ArF exposure. Generally, in etching insulating films, a fluorocarbon gas having high depositing property is used to form plasma, and etching is performed using the injection of ions having high energy. During such plasma etching having high deposition property and high energy, the surface roughness of the resist mask having been subjected to ArF exposure is increased through etching, and the increased surface roughness is transferred to the insulating film layer or layer to be etched, causing striation. Known methods for suppressing the increase of surface roughness of the photoresist layer through etching during the etching of insulating films using fluorocarbon plasma include, for example, the use of multilayered resists and the modification of surface material of the photoresist.
“Deposition control for reduction of 193 nm photoresist degradation in dielectric etching”, J. Vac. Sci. Technol. B23(1), January/February 2005, 217-223 (non-patent document 1) discloses a means for suppressing the increase of roughness of the photoresist layer during etching of the insulating film using fluorocarbon plasma.
However, such methods merely suppress the increase of surface roughness of the photoresist layer during etching of the insulating film using fluorocarbon plasma.
As described, in a plasma etching process having a low depositing property and low energy, such as the processing of gate electrodes of MOS transistors using fine photoresist circuit patterns, the problem of LER and LWR caused by unnecessary roughness formed on the surface and side walls of the photoresist circuit pattern prior to etching must be solved. The means for suppressing surface roughness in the etching of insulating films are not effective in solving the problems of unnecessary roughness formed on the surface and side walls of the photoresist circuit pattern prior to etching during the processing of gate electrodes.
As described, the problems of LER and LWR caused by unnecessary roughness formed on the surface and side walls of the photoresist circuit pattern prior to etching in the processing of gate electrodes of MOS transistors using fine photoresist circuit patterns have not yet been solved.